IS CS-2018S1-03

题目来源：Problem 3 日期：2024-08-07 题目主题：CS-数字电路-SRAM 设计

解题思路

我们需要设计一个简单的 SRAM（静态随机存取存储器）电路。问题分为三个部分：

1. 设计一个 2 位译码器，具有输入 $A_0$ 和 $A_1$，输出 $B_0$，$B_1$，$B_2$ 和 $B_3$。
2. 设计一个读数据的电路，利用第一个问题设计的译码器，从指定的存储单元中读取数据。
3. 在第二个问题的基础上，添加写数据的功能。

Solution

Question 1: 2-bit Decoder Design

A 2-bit decoder translates a 2-bit binary input into a one-hot encoded output. Here’s the design:

Truth Table

$A_1$	$A_0$	$B_3$	$B_2$	$B_1$	$B_0$
0	0	0	0	0	1
0	1	0	0	1	0
1	0	0	1	0	0
1	1	1	0	0	0

Logic Equations

$$\begin{array}{rl}{B}_0& =\overline{A_1}\cdot \overline{A_0}\\ B_1& =\overline{A_1}\cdot A_0\\ B_2& =A_1\cdot \overline{A_0}\\ B_3& =A_1\cdot A_0\end{array}$$

Circuit Diagram

Using basic gates (AND, OR, NOT):

• $B_0=\mathrm{NOT}(A_1)\mathrm{AND}\mathrm{NOT}(A_0)$
• $B_1=\mathrm{NOT}(A_1)\mathrm{AND}{A}_0$
• $B_2=A_1\mathrm{AND}\mathrm{NOT}(A_0)$
• $B_3=A_1\mathrm{AND}{A}_0$

Question 2: Reading Stored Data

Given the memory cells $V_{ij}$, we need to use the decoder to select the correct address and output the stored data.

Circuit Design

• Inputs: $A_0$, $A_1$
• Outputs: $V_0$, $V_1$, $V_2$, $V_3$

Each memory cell $V_{ij}$ outputs its value only when selected. The selection signal $S$ comes from the decoder outputs $B_0$, $B_1$, $B_2$, $B_3$.

For address selection:

$$\begin{array}{rl}{V}_0& =B_0\cdot V_{00}+B_1\cdot V_{10}+B_2\cdot V_{20}+B_3\cdot V_{30}\\ V_1& =B_0\cdot V_{01}+B_1\cdot V_{11}+B_2\cdot V_{21}+B_3\cdot V_{31}\\ V_2& =B_0\cdot V_{02}+B_1\cdot V_{12}+B_2\cdot V_{22}+B_3\cdot V_{32}\\ V_3& =B_0\cdot V_{03}+B_1\cdot V_{13}+B_2\cdot V_{23}+B_3\cdot V_{33}\end{array}$$

Question 3: Adding Write Functionality

To add the write functionality, we need to introduce a write signal $W_M$ and data inputs $U_0,U_1,U_2,U_3$.

Write Mechanism

• At the falling edge of $W_M$, the values of $U_j$ are stored in the memory cells $V_{ij}$ corresponding to the selected address $i$.

Circuit Design Modifications

• Inputs: $A_0$, $A_1$, $W_M$, $U_0$, $U_1$, $U_2$, $U_3$

Each memory cell $V_{ij}$ has a write input $W$. We need to generate the write signals from $W_M$ and the decoder outputs.

$$\begin{array}{rl}{W}_0& =W_M\cdot B_0\\ W_1& =W_M\cdot B_1\\ W_2& =W_M\cdot B_2\\ W_3& =W_M\cdot B_3\end{array}$$

When $W_i$ is active (falling edge of $W_M$), the values of $U_j$ are written to the corresponding memory cells $V_{ij}$.

知识点

译码器SRAM数字电路

难点思路

• 设计译码器的逻辑表达式并实现它
• 使用译码器选择正确的存储单元进行读取和写入操作

解题技巧和信息

• 理解译码器的基本功能和逻辑设计
• 通过逻辑门实现组合逻辑电路
• 利用时序逻辑控制存储单元的写入操作

重点词汇

• Decoder 译码器
• Memory Cell 存储单元
• Address 地址
• Write 写入
• Read 读取

参考资料

1. Digital Design by M. Morris Mano, Chap. 5
2. Fundamentals of Digital Logic with Verilog Design by Stephen Brown and Zvonko Vranesic, Chap. 3