2021S

Problem 1

In undirected graphs, a self-loop is an edge connecting the same vertex, and multi-edges are multiple edges connecting the same pair of vertices. From now on, we consider undirected graphs without self-loops and possibly with multi-edges. We say that a graph is an -graph if a graph consisting of a single edge can be obtained from by repeatedly applying the following two operations.

B-operation

When two multi-edges connect a pair of vertices, replace the multi-edges with a single edge connecting the pair of vertices.

C-operation

When one edge connects vertices and , another edge connects and (where ), and there is no other edge incident to , remove the vertex and replace the two edges with a new edge connecting and .

Answer the following questions.

  1. Let be a complete graph of vertices. Answer whether each of and is an -graph or not.

  2. Show that every -graph is planar.

  3. Give the maximum number of edges of an -graph with vertices without multi-edges, with a proof. Also, give such an -graph attaining the maximum for general , with an explanation.

  4. Give an -time algorithm which, given an undirected graph with vertices and edges as an input, determines whether it is an -graph or not. Explain also the graph data structures used in the algorithm for realizing -operations and -operations.


在无向图中,自环是连接同一顶点的边,多重边是连接同一对顶点的多条边。从现在起,我们考虑无自环且可能有多重边的无向图。我们说图 -图,如果通过重复应用以下两种操作,可以从 得到仅由一条边组成的图。

B-操作

当两条多重边连接一对顶点时,用连接该对顶点的一条边替换多重边。

C-操作

当一条边连接顶点 ,另一条边连接 (其中 ),且没有其他边与顶点 相连时,移除顶点 并用一条连接 的新边替换这两条边。

回答以下问题。

  1. 个顶点的完全图。回答 是否是 -图。

  2. 证明每个 -图都是平面的。

  3. 给出没有多重边的 个顶点的 -图的最大边数,并提供证明。此外,给出一个这样的 -图,其在一般 下达到最大值,并进行解释。

  4. 给出一个 时间复杂度的算法,该算法给定一个有 个顶点和 条边的无向图作为输入,确定它是否是 -图。还要解释实现 -操作和 -操作的图数据结构。


Problem 2

Let be the set of letters. For a word and two languages over , we define the language as follows, by induction on .

Here, represents the empty word. For example, if , , and , then . Furthermore, for languages , we define as . For example, if , , and , then .

Answer the following questions.

  1. Let , , and . Express using a regular expression.
  2. Let , , and . Express using a regular expression.
  3. Let , , and be deterministic finite automata, and for each , let be the language accepted by . Here, are the set of states, the transition function, the initial state, and the set of final states of (), respectively. Assume that the transition functions () are total. Give a non-deterministic finite automaton that accepts , with a brief explanation. You may use -transitions.
  4. For and () in question (3), give a deterministic finite automaton that accepts , with a brief explanation.

是字母集合 。对于一个单词 和两个语言 ,我们通过对 归纳来定义语言

这里, 表示空字。举例来说,如果 , , and ,那么 。此外,对于语言 ,我们定义 。例如,如果 , , 和 ,那么

回答以下问题。

  1. ,和 。用正则表达式表示
  2. ,和 。用正则表达式表示
  3. ,和 是确定有限自动机,并且对于每个 ,令 接受的语言。这里, 的状态集、转移函数、初始状态和终态集 (),分别。假设转移函数 () 是全函数。给出一个非确定有限自动机来接受 ,并简要解释。你可以使用 -转移。
  4. 对于问题 (3) 中的 (),给出一个确定有限自动机来接受 ,并简要解释。

Problem 3

Consider bit-serial communication circuits which send and receive 5-bit information bit-by-bit in a noisy environment. The 5-bit information consists of a 2-bit start-bit signal, 2-bit payload data, and a 1-bit odd-parity signal.

The sender circuit always outputs ‘0’ in the initial state. At the beginning of a communication, the sender outputs 2-bit data ‘11’ bit-by-bit. It subsequently outputs 2-bit payload data bit-by-bit from the most significant bit. It finally outputs an odd-parity signal such that the number of ‘1’s in the sent bit sequence including the 2-bit start-bit signal, the payload data, and the parity signal itself is an odd number. After sending the parity signal, the sender circuit goes to the initial state, and it outputs ‘0’ until the next sending.

The receiver circuit has a 1-bit input A from the sender circuit, a 1-bit output B for the parity check result, and a 2-bit output for the received payload data. It obtains payload data from a received bit sequence and does the odd parity checking.

In the initial state, the receiver circuit waits for ‘1’ corresponding to the first bit of a start-bit signal. In the next clock cycle after receiving the first bit of a start-bit signal, it receives a value corresponding to the second bit of a start-bit signal. If the received value corresponding to the second bit of a start-bit signal is ‘0’, the receiver circuit judges that the first received bit ‘1’ was an error caused by a noise, and goes back to the initial state. Otherwise, in the next 2 clock cycles, it stores each value of the input A as payload data. At the next clock cycle, it receives a parity-bit, and it verifies that the number of ‘1’s in the received 5-bit sequence consisting of the 2-bit start-bit signal, the 2-bit payload data, and the parity-bit is odd. It assigns ‘1’ to the output B if the number of ‘1’s is odd, and it assigns ‘0’ otherwise. The value of the output B is always ‘0’, except in the clock cycles for receiving a parity-bit. The receiver circuit then goes to the initial state, regardless of the parity-check result.

Answer the following questions.

  1. Give the state transition diagram of a Mealy-type finite state machine (FSM), consisting of 7 states, for the parity check circuit with the input A and the output B in the receiver circuit. Based on the state transition diagram, give also a corresponding state transition table and an output table by using the one-hot encoding. One-hot encoding is a method for encoding each state as a bit sequence where only one bit is ‘1’ and the other bits are ‘0’.

  2. Based on the state transition table and the output table in question (1), express the output B as a Boolean expression in terms of the input A and the one-hot encoding representation of the current state of the FSM. Based on the Boolean expression, give also a corresponding gate-level circuit of the parity check circuit that outputs B, given A and the one-hot encoding representation of the current state of the FSM as inputs. You are allowed to use only 2-input AND gates, 2-input OR-gates, and NOT-gates. There is no limitation on the number of gates. You need not describe unused input signals.

  3. According to the Boolean expression answered in question (2), give a CMOS transistor level circuit that outputs B, given A and the one-hot encoding representation of the current state of the FSM as inputs. You are not allowed to use more than 12 transistors. You may use the inverter mark, but the number of transistors required for the inverters must be included in the total number of transistors. You need not describe unused input signals.


考虑在嘈杂环境中按位发送和接收 5 位信息的位序列通信电路。5 位信息由 2 位起始信号、2 位有效载荷数据和 1 位奇校验信号组成。

发送电路在初始状态下总是输出 ‘0’。在通信开始时,发送电路按位输出 2 位数据 ‘11’。随后按位输出 2 位有效载荷数据,从最高有效位开始。最后输出一个奇校验信号,使得包括 2 位起始信号、有效载荷数据和校验信号在内的发送位序列中的 ‘1’ 的数量为奇数。发送校验信号后,发送电路进入初始状态,并在下次发送前输出 ‘0’。

接收电路从发送电路接收 1 位输入 A,输出用于校验结果的 1 位输出 B,以及用于接收的有效载荷数据的 2 位输出。它从接收的位序列中获取有效载荷数据并进行奇校验。

在初始状态下,接收电路等待与起始信号的第一位相对应的 ‘1’。在接收到起始信号的第一位后的下一个时钟周期内,它接收与起始信号的第二位相对应的值。如果接收到的与起始信号的第二位相对应的值为 ‘0’,接收电路判断第一个接收到的 ‘1’ 是由噪声引起的错误,并返回初始状态。否则,在接下来的 2 个时钟周期内,它将每个输入 A 的值存储为有效载荷数据。在下一个时钟周期内,它接收一个校验位,并验证接收的 5 位序列(包括 2 位起始信号、2 位有效载荷数据和校验位)中的 ‘1’ 的数量是否为奇数。如果 ‘1’ 的数量为奇数,则将 ‘1’ 分配给输出 B,否则分配 ‘0’。输出 B 的值总是为 ‘0’,除了接收校验位的时钟周期外。接收电路然后返回初始状态,无论校验结果如何。

回答以下问题。

  1. 给出一个包含 7 个状态的 Mealy 型有限状态机(FSM)的状态转换图,用于接收电路中的校验电路,输入为 A,输出为 B。基于状态转换图,使用独热编码给出相应的状态转换表和输出表。独热编码是一种将每个状态编码为仅一个比特为 ‘1’ 而其他比特为 ‘0’ 的方法。

  2. 基于问题(1)中的状态转换表和输出表,用布尔表达式表示输出 B,作为输入 A 和 FSM 当前状态的独热编码表示的函数。基于布尔表达式,给出相应的门级电路,该电路输出 B,输入为 A 和 FSM 当前状态的独热编码表示。你可以使用的门电路包括 2 输入 AND 门、2 输入 OR 门和 NOT 门。门电路数量没有限制。无需描述未使用的输入信号。

  3. 根据问题(2)中回答的布尔表达式,给出一个 CMOS 晶体管级电路,该电路输出 B,输入为 A 和 FSM 当前状态的独热编码表示。你不能使用超过 12 个晶体管。你可以使用反相器标记,但反相器所需的晶体管数量必须包括在晶体管总数中。无需描述未使用的输入信号。


Problem 4

Let be the set of real numbers. Denote by the transposition operator of a vector and a matrix. When is a -dimensional column vector, the norm is defined by . Define the inner product of two column vectors as . For a matrix , define . Let be the trace of the matrix .

Consider the problem of predicting a real-valued label from a -dimensional real vector . For learning a predictor, suppose that training samples

are given where means that is the real-valued label of . In addition, by using a -dimensional vector and observational noise that is independent and identically distributed, assume the data generation process as

where the expectation and variance . Let us introduce the symbols

We also use the symbol where is assumed to be a regular matrix. The expectation over the observational noises is expressed by .

We formulate the learning of a predictor as the following optimization problem.

Answer the following questions. Describe not only an answer but also the derivation process.

  1. Express using , and .

  2. Suppose we wish to express in the form of . Express the matrix and the positive real number using and .

  3. Suppose we wish to express in the form of . Express the matrix using the matrix .

  4. Explain what problem arises when is not a regular matrix and suggest a way to remedy the problem.


是实数集。用 表示向量和矩阵的转置运算符。当 是一个 维列向量时,范数 定义为 。定义两个列向量 的内积为 。对于 矩阵 ,定义 。设 为矩阵 的迹。

考虑从 维实向量 预测实值标签 的问题。为了学习一个预测器,假设有 个训练样本

其中 表示 的实值标签。此外,使用 维向量 和观测噪声 ,假设数据生成过程为

其中期望 和方差 . 我们引入符号

我们还使用符号 ,假设 是一个正规矩阵。观测噪声的期望用 表示。

我们将预测器 的学习公式化为以下优化问题。

回答以下问题。描述不仅是答案,还有推导过程。

  1. 表示

  2. 假设我们希望以 的形式表示 。用 表示矩阵 和正实数

  3. 假设我们希望以 的形式表示 。用矩阵 表示矩阵

  4. 解释当 不是正规矩阵时会出现什么问题,并提出解决该问题的方法。